1. Field of Invention
The present invention relates to a method for manufacturing semiconductor devices. More particularly, the present invention relates to a method for forming landing pads in semiconductor devices.
2. Description of Related Art
As integrity of the integrated circuits increases, less and less area can be used to manufacture interconnects. For very large scale integration (VLSI) ICs, a multilevel interconnect structure, including two or more levels of metal-interconnect structures that serve as wiring line structures for electrically interconnecting the various components in the integrated circuits, are typically formed.
However, the multilevel interconnect structure increases aspect ratios for contact openings due to the increased height in the semiconductor devices. Because of the increased aspect ratios, the alignment window and the etching window for the contact opening become smaller. For overcoming this problem, a self-aligned contact process has been developed. The self-aligned contact (SAC) process has been widely used in manufacturing the landing pad in the dynamic random access memory (DRAM) device.
FIG. 1A to FIG. 1D are cross-sectional views illustrating the process steps of manufacturing the prior art landing pad in the DRAM device.
Referring to FIG. 1A, a semiconductor substrate 100 is provided with shallow trench isolation (STI) structures 110, gate structures 127, a common source region 130 and drain regions 132 formed therein. The gate structure 127 includes a gate oxide layer 122, a polysilicon layer (wordline) 120, a nitride cap layer 124 and nitride spacers 126.
Referring to FIG. 1B, a first dielectric layer 140 is deposited over the substrate 100. For example, the first dielectric layer 140 is a silicon oxide layer formed by chemical vapor deposition (CVD). A patterned photoresist layer 145 is formed on the first dielectric layer 140. Using the patterned photoresist layer 145 as an etching mask, an anisotropic etching step, such as a dry etching step, is performed to remove a portion of the first dielectric layer 140 until the substrate is exposed. Next, the patterned photoresist layer 145 is removed, and self-aligned contact openings 148 are formed.
Referring to FIG. 1C, a polysilicon layer 150 is deposited over the substrate 100 and fills the self-aligned contact openings 148. Using the first dielectric layer 140 as a polishing stop layer, a chemical mechanical polishing (CMP) step is performed to remove a portion of the polysilicon layer 150 above the first dielectric layer 140, so that landing pads 150 are formed inside the self-aligned contact opening 148.
Referring to FIG. 1D, after forming the landing pads 150, a second dielectric layer 160 is formed over the substrate 100. After a bitline opening 170 is formed in the second dielectric layer 160 above the common source region 130, a conductive material is filled in the bitline opening 170 to form a bitline 175. Afterwards, a third dielectric layer 180 is formed to cover the second dielectric layer 170 and the bitline 175. After node contact openings 185 are formed through the third dielectric layer 180 and the second dielectric layer 170 above the drain regions 132, a conductive material is filled into the node contact openings 185 to form lower electrodes (not shown) for the DRAM cell.
As cited above, the SAC process is used to form the self-aligned contact opening. Even though the SAC opening can increase the etching window and the alignment window for forming the bitline opening and the node contact opening in the following processes, the SAC process, including depositing, photolithography and etching, also complicate the whole processes.
The invention provides a method for forming landing pads in the semiconductor devices. The present invention can reduce steps of the SAC process, thus increasing stability of the semiconductor devices and reducing costs.
As embodied and broadly described herein, the invention provides a method for landing pads in the semiconductor devices, comprising the following steps: providing a semiconductor substrates with a plurality of active regions, a plurality of gate structures above the active regions and a plurality of source/drain regions, while each gate structure comprises a top cap layer and sidewall spacers; forming a conductive layer over the substrate; removing a portion of the conductive layer above the gate structure using the top cap layer of the gate structure as a stop layer, so that a height of the conductive layer is lower than a height of the gate structure; forming a patterned mask layer, right above the active regions, over the substrate; performing an etching step to define the conductive layer above the active regions; and removing the patterned mask layer and forming landing pads on the active regions.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.